/*Yipeng Huang and Scott Rogowski*/
/*yh2315 smr2167*/

//A file of registers
module DelayRegisterFile (clk, reset, pause, data, q);
	
	parameter WIDTH = 32; // default value
	
	input clk;
	input reset;
	input pause;
	input [WIDTH-1:0] data;

	output [WIDTH-1:0] q;
	
	FF ffs [WIDTH-1:0] (.clk(clk), .reset(reset), .enable(!pause), .set(data[WIDTH-1:0]), .q(q[WIDTH-1:0]));
	//TODO: Check that holding on to data between stages like this properly stalls pipeline; data doesn't go in to register, but still goes out.
	
	endmodule
